Integrated circuits, in particular high-speed CMOS circuits, are susceptible to electrostatic discharge (ESD) damage when exposed to an ESD event. Such events occur during packaging and assembly of the integrated circuit as well as in the field during use of the circuitry. Currently a special protection circuit such as diodes and/or transistors are placed at the circuit peripheral nodes (e.g., leads or pads) to clamp the high voltage of an ESD event to a level that will not damage the circuitry within the integrated circuit. As circuit speed increases, device feature size is reduced. However, this is not true for the ESD protection circuits, which cannot be scaled to a smaller size if the same level of ESD protection must be maintained. Furthermore, as feature size decreases and circuit speed increases, parasitic capacitance of these ESD protection circuits becomes detrimental to circuit performance.
Additionally, as integrated circuit size has reduced, the packaging has also been reduced in size. The use of Controlled Collapsed Chip Connections (C4), also known as flip chip technology, has found widespread use to provide improved electrical interconnect performance for small integrated circuit packages. Where the pitch of connections has been reduced to 50 micrometers, C4NP (C4 New Process) can be used to provide connectivity. With such a small pitch, there is no room on an integrated circuit to include ESD protection devices having a level of ESD protection commensurate with the protection level provided to the larger devices of the past.
Therefore, there is a need in the art for an ESD protection technique that does not rely on active devices to protect the integrated circuit from ESD events during packaging and assembly.